This invention relates to techniques for forming self-aligned semiconductor devices and components for monolithographic integrated circuits. More particularly, the invention relates to a method of forming a self-aligned metal oxide semiconductor field effect transistor (MOSFET) having low junction leakage and a low percentage of shorting between the gate and the source/drain regions. The method uses two layers of dielectric film on the edge of the gate. The first layer forms a sidewall oxide used in making the lightly doped drain (LDD) structure. The second layer functions as an extended spacer to isolate the subsequently formed silicided regions from the highly doped regions. This technique forms a novel double spacer self-aligned silicide MOS structure (DSS MOS) useful for high density very large scale integrated (VLSI) circuit technology.
Self-aligned techniques have been the preferred technology for forming integrated circuits and their constituent devices and elements because of their simplicity and their ability to form high density integrated circuit (IC) devices. William D. Ryden et al., U.S. Pat. No. 4,486,943, proposed a method of fabricating a MOS transistor having a gate electrode and self-aligned source/drain region with zero overlap. A relatively thick oxide layer is thermally grown on the top and sides of a polycrystalline silicon gate. During the implantation, the thick layers act as masks to define the source/drain regions and, after heat driving, the implanted regions are substantially aligned with the gate electrode. No extra mask layer is needed to define the self-aligned source and drain regions.
As device dimensions decrease, both vertically and laterally, many problems arise, especially those caused by the increase of sheet resistance of the interconnect lines and to the source/drain regions. The increase of resistance dramatically degrades the device performance and becomes a crucial factor in device processing. To overcome this problem, researchers have incorporated refractory metal silicides into the device fabricating process; see S. P. Murarka, "Refractory Silicides for Integrated Circuits," J. Vac. Sci. Technol., 17(4) (July/August 1980), pp. 775-791.
At the gate level, refractory metal silicides have received the major attention because of their compatibility with silicon gate device processing requirements. B. L. Crowder et al., "1 um MOSFET VISI Technology: Part VII--Metal Silicide Interconnection Technology--A Future Perspective" (IEEE Transactions on Electron Devices, Vol. ED-26, No. 4 (April 1979), pp. 369-371) describes the combination of silicide and polycrystalline silicon (polycide) instead of conventional polycrystalline silicon for gate interconnects in VLSI device processing to decrease the sheet resistance. For the source/drain regions, J. -S. Chang et al., U.S. Pat. No. 4,478,679, proposed a self-aligning process for forming a barrier metal over the source/drain regions. Initially, a layer of oxide is deposited over the entire surface. The layer is then removed, except from the side surfaces of the upwardly protruding gate region. Thereafter, successive layers of barrier metal and organic material are deposited over the surface. The organic material is removed to expose the barrier metal in all areas, except over depressed source and drain regions; and finally, the exposed barrier metal and the remaining organic is stripped, leaving barrier metal only on the surface of the source and drain regions. Unfortunately, this method does not provide the low gate and source/drain resistance simultaneously and the use of the organic material may dramatically contaminate the barrier metal.
A. F. Tasch, Jr. et al., U.S. Pat. No. 4,384,301, disclosed a high performance submicron MOSFET device structure which shows the simultaneous silicidation of the source/drain and gate regions. The silicide source and drain regions define a channel region and are isolated from the gate by insulating layers (spacers) on the edges of the gate electrode. The spacers are formed by first growing or depositing an oxide over the structure including the gate electrode, argon-implanting the oxide to a specific depth, and etching the structure so that the oxide remains only on the edges of the gate electrode region. The etchant etches the implanted areas at a high rate than the unimplanted areas. It is claimed that the thicker oxide at the edges of the gate increases the breakdown voltage between different levels of interconnections and between the gate and the source and drain. The metal silicide regions are formed simultaneously by sputtering or evaporating metal upon the device after the source and drain are formed. The device is annealed at a high temperature to cause the metal to react with the silicon to form the silicide. After annealing, the metal not exposed to silicon is removed. This process shows the use of silicide self-aligned source/drain and gate technology.
Although U.S. Pat. No. 4,384,301 shows the advantages of self-aligning and of low resistance of gate and source/drain in MOS technology, many problems still exist because shorter spaces and shallower junctions are needed to properly scale down the devices. If the length of sidewall oxide is to be reduced, isolating the gate and source/drain regions during the silicidation process becomes extremely difficult because of the lateral diffusion of the silicon and the metal along the sidewall oxide. This will result in shorting of gate and source/drain areas. It will be understood that the limit on the length of spacer is dependent on the temperature of metal/silicon reaction and the thickness of the metal film deposited.
The problem is especially severe for MOS devices using LDD structures with the self-aligned silicidation of the gate and source/drain regions. If the spacer described in U.S. Pat. No. 4,384,301 were used, the damage induced by the ion implantation of the silicon, coupled with the high stress of the silicided gate and source/drain regions, would induce significant damage near and under the spacer. This would result in high junction leakage and low electrostatic discharge (ESD) protection in the devices and circuits utilizing such devices.